Philippe Lorenzini

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 5

Top Topics

Silicon On Insulator

Memory Capacity

Top Venues

J. Low Power Electron.

J. Syst. Archit.

Microprocess. Microsystems

Publications

Radouane Habhab, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa
40nm SONOS Embedded Select in Trench Memory. ESSDERC (2023)
Paul Devoge, Hassen Aziza, Philippe Lorenzini, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. ISCAS (2022)
Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel
A Schmitt trigger to benchmark the performance of a new zero-cost transistor. ICECS 2022 (2022)
Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel
Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. DTIS (2021)
Zhaopeng Wei, Gilles Jacquemod, Philippe Lorenzini, Frédéric Hameau, Emeric de Foucauld, Yves Leduc
Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology. J. Low Power Electron. 12 (1) (2016)
Alexandre Fonseca, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Philippe Lorenzini
VCO design in SOI technologies. NEWCAS (2014)
Alexandre Fonseca, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod
Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop. J. Low Power Electron. 10 (1) (2014)
François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini
Design space exploration for partially reconfigurable architectures in real-time systems. J. Syst. Archit. 59 (8) (2013)
François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah, Serge Weber, Philippe Lorenzini
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. Microprocess. Microsystems 37 (1) (2013)
François Duhem, Fabrice Muller, Philippe Lorenzini
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. IET Comput. Digit. Tech. 6 (2) (2012)
François Duhem, Fabrice Muller, Philippe Lorenzini
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. ARC (2011)
François Duhem, Fabrice Muller, Philippe Lorenzini
Methodology for designing partially reconfigurable systems using transaction-level modeling. DASIP (2011)