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Layout optimizations to decrease internal power and area in digital CMOS standard cells.

Jordan InnocentiFranck JulienJean-Michel PortalLaurent LopezQ. HubertPascal MassonJacques SonzogniStephan NielArnaud Régnier
Published in: MIPRO (2015)
Keyphrases
  • power consumption
  • circuit design
  • low power
  • high speed
  • neural network
  • genetic algorithm
  • image processing
  • power management
  • power reduction
  • data sets
  • image sequences
  • digital images
  • digital media
  • internal and external