Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Jordan InnocentiLoic WelterFranck JulienLaurent LopezJacques SonzogniStephan NielArnaud RégnierEmmanuel PaireKaren LaboryEric DenisJean-Michel PortalPascal MassonPublished in: MWSCAS (2014)
Keyphrases
- power reduction
- power consumption
- low power
- nm technology
- cmos technology
- power dissipation
- clock gating
- design process
- case study
- metal oxide semiconductor
- power saving
- high speed
- low cost
- embedded systems
- energy efficiency
- cost effective
- peer to peer
- single chip
- main memory
- data management
- user interface
- database systems