Richard G. Southwick

Publication Activity (10 Years)

Years Active: 2017-2021
Publications (10 Years): 9

Top Topics

Silicon Dioxide

Automatic Analysis

Leakage Current

Top Venues

Publications

Huimei Zhou, Miaomiao Wang, Ruqiang Bao, Tian Shen, Ernest Wu, Richard G. Southwick, Jingyun Zhang, Veeraraghavan S. Basker, Dechao Guo
TDDB Reliability in Gate-All-Around Nanosheet. IRPS (2021)
Nilotpal Choudhury, Tarun Samadder, Ravi Tiwari, Huimei Zhou, Richard G. Southwick, Miaomiao Wang, Souvik Mahapatra
Analysis of Sheet Dimension (W, L) Dependence of NBTI in GAA-SNS FETs. IRPS (2021)
Huimei Zhou, Miaomiao Wang, Jingyun Zhang, Koji Watanabe, Curtis Durfee, Shogo Mochizuki, Ruqiang Bao, Richard G. Southwick, Maruf Bhuiyan, Basker Veeraraghavan
NBTI Impact of Surface Orientation in Stacked Gate-All-Around Nanosheet Transistor. IRPS (2020)
Nilotpal Choudhury, Uma Sharma, Huimei Zhou, Richard G. Southwick, Miaomiao Wang, Souvik Mahapatra
Analysis of BTI, SHE Induced BTI and HCD Under Full VG/VD Space in GAA Nano-Sheet N and P FETs. IRPS (2020)
Narendra Parihar, Uma Sharma, Richard G. Southwick, Miaomiao Wang, James H. Stathis, Souvik Mahapatra
On the Frequency Dependence of Bulk Trap Generation During AC Stress in Si and SiGe RMG P-FinFETs. IRPS (2019)
Miaomiao Wang, Jingyun Zhang, Huimei Zhou, Richard G. Southwick, Robin Hsin Kuo Chao, Xin Miao, Veeraraghavan S. Basker, Tenko Yamashita, Dechao Guo, Gauri Karve, Huiming Bu, James H. Stathis
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor. IRPS (2019)
Miaomiao Wang, Richard G. Southwick, Kangguo Cheng, James H. Stathis
Lateral profiling of HCI induced damage in ultra-scaled FinFET devices with Id-Vd characteristics. IRPS (2018)
Miaomiao Wang, Xin Miao, James H. Stathis, Richard G. Southwick
Hot carrier reliability in ultra-scaled sige channel p-FinFETs. ASICON (2017)
ChoongHyun Lee, Richard G. Southwick, Shogo Mochizuki, Paul Jamison, Ruqiang Bao, Rajan Pandey, Aniruddha Konar, Takashi Ando, Vijay Narayanan, Bala Haran, Hemanth Jagannathan
Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS. ASICON (2017)