Georg Georgakos

Publication Activity (10 Years)

Years Active: 2003-2019
Publications (10 Years): 3

Top Topics

Error Correcting

High Reliability

Model Based Diagnosis

Digital Circuits

Top Venues

Publications

Christian Schlünder, Katja Waschneck, Peter Rotter, Susanne Lachenmann, Hans Reisinger, Franz Ungar, Georg Georgakos
From Device Aging Physics to Automated Circuit Reliability Sign Off. IRPS (2019)
A. Klockmann, Georg Georgakos, Michael Gössel
A new 3-bit burst-error correcting code. IOLTS (2017)
Nasim Pour Aryan, Christian Funke, Jens Bargfrede, Cenk Yilmaz, Doris Schmitt-Landsiedel, Georg Georgakos
In situ measurement of aging-induced performance degradation in digital circuits. ETS (2016)
Rolf-Peter Vollertsen, Georg Georgakos, K. Kölpin, C. Olk
A fWLR test structure and method for device reliability monitoring using product relevant circuits. IRPS (2015)
Nasim Pour Aryan, Nils Heidmann, Martin Wirnshofer, Nico Hellwege, Jonas Pistor, Dagmar Peters-Drolshagen, Georg Georgakos, Steffen Paul, Doris Schmitt-Landsiedel
Power efficient digital IC design for a medical application with high reliability requirements. PATMOS (2014)
Nasim Pour Aryan, A. Listl, Leonhard Heiß, Cenk Yilmaz, Georg Georgakos, Doris Schmitt-Landsiedel
From an analytic NBTI device model to reliability assessment of complex digital circuits. IOLTS (2014)
Georg Georgakos, Ulf Schlichtmann, Reinhard Schneider, Samarjit Chakraborty
Reliability challenges for electric vehicles: from devices to architecture and systems software. DAC (2013)
Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel
Reliability monitoring of digital circuits by in situ timing measurement. PATMOS (2013)
Martin Wirnshofer, Nasim Pour Aryan, Leonhard Heiß, Doris Schmitt-Landsiedel, Georg Georgakos
Delay Monitoring to Adapt for Pvta variations. J. Circuits Syst. Comput. 21 (8) (2012)
Martin Wirnshofer, Leonhard Heiß, Anil Narayan Kakade, Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel
Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. DDECS (2012)
Martin Wirnshofer, Leonhard Heiß, Georg Georgakos, Doris Schmitt-Landsiedel
A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring. DDECS (2011)
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene). it Inf. Technol. 52 (4) (2010)
Stefan Drapatz, Thomas Fischer, Karl Hofmann, Ettore Amirante, Peter Huber, Martin Ostermayr, Georg Georgakos, Doris Schmitt-Landsiedel
Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation. ESSCIRC (2009)
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
Aging analysis of circuit timing considering NBTI and HCI. IOLTS (2009)
Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel
A Design Space Comparison of 6T and 8T SRAM Core-Cells. PATMOS (2008)
Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations. IEEE J. Solid State Circuits 42 (7) (2007)
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. IEEE J. Solid State Circuits 42 (1) (2007)
Franz X. Ruckerbauer, Georg Georgakos
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena. IOLTS (2007)
Florian Bauer, Klaus von Arnim, Christian Pacha, Thomas Schulz, Michael Fulde, Axel Nackaerts, M. Jurczak, Wade Xiong, K. T. San, C. Rinn Cleavelin, Klaus Schruefer, Georg Georgakos, Doris Schmitt-Landsiedel
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies. ESSCIRC (2007)
Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead. IEEE J. Solid State Circuits 41 (7) (2006)
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions. ISSCC (2006)
Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme. ESSCIRC (2005)
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. PATMOS (2004)
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. PATMOS (2004)
Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes. VLSI-SoC (Selected Papers) (2003)
Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. VLSI-SOC (2003)