Login / Signup

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies.

Florian BauerKlaus von ArnimChristian PachaThomas SchulzMichael FuldeAxel NackaertsM. JurczakWade XiongK. T. SanC. Rinn CleavelinKlaus SchrueferGeorg GeorgakosDoris Schmitt-Landsiedel
Published in: ESSCIRC (2007)
Keyphrases
  • power consumption
  • field effect transistors
  • leakage current
  • data mining
  • random access memory
  • parameter settings
  • low power
  • web intelligence
  • high density
  • fine tuning
  • cmos technology
  • layout design