Mayukh Bhattacharya

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 7

Top Topics

Analog Circuits

Test Generation

Frequency Response

Fault Diagnosis

Top Venues

J. Electron. Test.

Publications

Sayandeep Sanyal, Mayukh Bhattacharya, Pallab Dasgupta, Amit Patra
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection. VLSID (2023)
Jonti Talukdar, Arjun Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty
Automatic Structural Test Generation for Analog Circuits using Neural Twins. ITC (2022)
Mayukh Bhattacharya, Beatrice Solignac, Michael Dürr
Application of Sampling in Industrial Analog Defect Simulation. ITC (2022)
Sayandeep Sanyal, Mayukh Bhattacharya, Amit Patra, Pallab Dasgupta
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits. J. Electron. Test. 36 (6) (2020)
Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits. ATS (2019)
Sayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis. ACM Great Lakes Symposium on VLSI (2019)
Anandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti
Innovative practices on functional testing and fault simulation for FuSa. VTS (2018)
Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya
Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. VLSI Design (2001)
Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. IEEE J. Solid State Circuits 36 (6) (2001)
Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González, Pinaki Mazumder
A 250-MHz, 32-bit quantum MOS correlator prototype. ICECS (2001)
Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. VLSI Design (2001)
Mayukh Bhattacharya, Pinaki Mazumder
Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta
A physical design tool for built-in self-repairable RAMs. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. ISMVL (2000)
Mayukh Bhattacharya, Pinaki Mazumder
Convergence Issues in Resonant Tunneling Diode Circuit Simulation. VLSI Design (2000)
Mayukh Bhattacharya, Shriram Kulkarni, Alejandro F. González, Pinaki Mazumder
A prototyping technique for large-scale RTD-CMOS circuits. ISCAS (2000)
Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
A Physical Design Tool for Built-in Self-Repairable Static RAMs. DATE (1999)
Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González
Circuit Design using Resonant Tunneling Diodes. VLSI Design (1998)
Mayukh Bhattacharya, Pinaki Mazumder
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. Great Lakes Symposium on VLSI (1998)
Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Jian Ping Sun, George I. Haddad
Digital circuit applications of resonant tunneling devices. Proc. IEEE 86 (4) (1998)