Jin-Tai Yan

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 29

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ACM Trans. Design Autom. Electr. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Integr.

Publications

Chia-Heng Yen, Jin-Tai Yan
Design and analysis of sum-prediction adder. Integr. 96 (2024)
Chia-Heng Yen, Jin-Tai Yan
Layer-Minimization-Oriented GNR Area Routing. ICECS (2023)
Jin-Tai Yan
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Jin-Tai Yan
Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Jin-Tai Yan
Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Very Large Scale Integr. Syst. 30 (10) (2022)
Jin-Tai Yan
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs. IEEE Trans. Very Large Scale Integr. Syst. 29 (11) (2021)
Jin-Tai Yan
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Jin-Tai Yan
Fuzzy-Clustering-Based Circular Topological Via Minimization in PCB Designs. IEEE Trans. Fuzzy Syst. 29 (5) (2021)
Jin-Tai Yan
Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Jin-Tai Yan, Po-Yuan Huang, Chia-Hsun Yen
Efficient Standard-Cell Legalization for Minimization of Total Movement. ICECS (2021)
Jin-Tai Yan
Delay-Constrained GNR Routing for Layer Minimization. IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Jin-Tai Yan, Po-Yuan Huang, Chien-Yi Wang
Construction of Obstacle-Avoiding Delay-Driven GNR Routing Tree. TENCON (2020)
Jin-Tai Yan
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Jin-Tai Yan
Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment. ACM Trans. Design Autom. Electr. Syst. 25 (2) (2020)
Jin-Tai Yan
Single-Layer GNR Routing for Minimization of Bending Delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Jin-Tai Yan
Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (3) (2019)
Jin-Tai Yan, Chia-Heng Yen
Construction of Delay-Driven GNR Routing Tree. NEWCAS (2019)
Jin-Tai Yan
Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing. ACM Trans. Design Autom. Electr. Syst. 24 (6) (2019)
Jin-Tai Yan
Direction-Constrained Rectangle Escape Routing. ACM Trans. Design Autom. Electr. Syst. 23 (3) (2018)
Jin-Tai Yan, Chia-Heng Yen
Feasible Assignment of Micro-Bumps in 3D ICs. NEWCAS (2018)
Jin-Tai Yan
On-Chip Optical Channel Routing for Signal Loss Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (8) (2018)
Jin-Tai Yan
One-Sided Net Untangling With Internal Detours for Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (6) (2017)
Jin-Tai Yan
Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs. ACM Trans. Design Autom. Electr. Syst. 22 (3) (2017)
Jin-Tai Yan
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs. ACM Trans. Design Autom. Electr. Syst. 21 (2) (2016)
Jin-Tai Yan, Meng-Tian Chen, Chia-Heng Yen
Cell-aware MBFF utilization for clock power reduction. ICECS (2016)
Jin-Tai Yan
Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (8) (2016)
Jin-Tai Yan
Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs. Integr. 49 (2015)
Jin-Tai Yan
Length-constrained escape routing of differential pairs. Integr. 48 (2015)
Jin-Tai Yan
Single-layer obstacle-aware routing for substrate interconnections. Integr. 51 (2015)
Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen
Feasible region assignment of routing nets in single-layer routing. ISCAS (2014)
Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen
Efficient micro-bump assignment for RDL routing in 3DICs. ICECS (2014)
Jin-Tai Yan
Fault-tolerant analysis of TMR design with noise-aware logic. Integr. 47 (4) (2014)
Jin-Tai Yan, Zhi-Wei Chen
Post-layout redundant wire insertion for fixing min-delay violations. ISCAS (2013)
Zhi-Wei Chen, Jin-Tai Yan
Routability-constrained multi-bit flip-flop construction for clock power reduction. Integr. 46 (3) (2013)
Zhi-Wei Chen, Jin-Tai Yan
Timing-constrained replacement using spare cells for design changes. ACM Great Lakes Symposium on VLSI (2013)
Jin-Tai Yan, Zhi-Wei Chen
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ACM Great Lakes Symposium on VLSI (2013)
Zhi-Wei Chen, Jin-Tai Yan
Utilization of multi-bit flip-flops for clock power reduction. ICECS (2012)
Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen
Density-reduction-oriented layer assignment for rectangle escape routing. ACM Great Lakes Symposium on VLSI (2012)
Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen
Top-down-based symmetrical buffered clock routing. ACM Great Lakes Symposium on VLSI (2012)
Jin-Tai Yan, Zhi-Wei Chen
Post-layout OPE-predicted redundant wire insertion for clock skew minimization. ICCD (2012)
Jin-Tai Yan, Zhi-Wei Chen
New optimal layer assignment for bus-oriented escape routing. Integr. 45 (3) (2012)
Jin-Tai Yan, Chia-Han Kao, Ming-Chien Huang, Zhi-Wei Chen
Efficient assignment of inter-die signals for die-stacking SiP design. ISCAS (2012)
Jin-Tai Yan
Resource-constrained link insertion for delay reduction. Integr. 45 (4) (2012)
Jin-Tai Yan, Zhi-Wei Chen
Direction-constrained layer assignment for rectangle escape routing. SoCC (2012)
Jin-Tai Yan, Zhi-Wei Chen
Pre-assignment RDL routing via extraction of maximal net sequence. ICCD (2011)
Jin-Tai Yan, Zhi-Wei Chen
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. DATE (2011)
Jin-Tai Yan, Zhi-Wei Chen
New optimal layer assignment for bus-oriented escape routing. ACM Great Lakes Symposium on VLSI (2011)
Jin-Tai Yan, Zhi-Wei Chen
Obstacle-aware length-matching bus routing. ISPD (2011)
Zhi-Wei Chen, Jin-Tai Yan
Timing-constrained I/O buffer placement for flip-chip designs. DATE (2011)
Jin-Tai Yan
IO connection assignment and RDL routing for flip-chip designs. ACM Trans. Design Autom. Electr. Syst. 16 (4) (2011)
Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen
Simultaneous escape routing based on routability-driven net ordering. SoCC (2011)
Jin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen
Thermal via planning for temperature reduction in 3D ICs. SoCC (2010)
Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen
Ordered escape routing via routability-driven pin assignment. ACM Great Lakes Symposium on VLSI (2010)
Jin-Tai Yan, Zhi-Wei Chen
Resource-constrained timing-driven link insertion for critical delay reduction. ACM Great Lakes Symposium on VLSI (2010)
Zhi-Wei Chen, Jin-Tai Yan
Width-constrained wire sizing for non-tree interconnections. ISCAS (2010)
Jin-Tai Yan, Kai-Ping Lu, Zhi-Wei Chen
Routability-driven partitioning-based IO assignment for flip-chip designs. APCCAS (2010)
Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen
Routability-driven RDL routing with pin reassignment. SoCC (2010)
Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen
Obstacle-aware longest path using rectangular pattern detouring in routing grids. ASP-DAC (2010)
Jin-Tai Yan, Zhi-Wei Chen
Low-cost low-power bypassing-based multiplier design. ISCAS (2010)
Jin-Tai Yan, Zhi-Wei Chen
Two-sided single-detour untangling for bus routing. DAC (2010)
Zhi-Wei Chen, Jin-Tai Yan
Routability-driven flip-flop merging process for clock power reduction. ICCD (2010)
Jin-Tai Yan, Zhi-Wei Chen
IO connection assignment and RDL routing for flip-chip designs. ASP-DAC (2009)
Zhi-Wei Chen, Jin-Tai Yan, Hsing-Lin Ko
Accurate Transformation-based Timing Analysis for RC Non-tree Circuits. ISCAS (2009)
Jin-Tai Yan, Zhi-Wei Chen
Low-power multiplier design with row and column bypassing. SoCC (2009)
Jin-Tai Yan, Zhi-Wei Chen
Redundant wire insertion for yield improvement. ACM Great Lakes Symposium on VLSI (2009)
Jin-Tai Yan, Zhi-Wei Chen
RDL pre-assignment routing for flip-chip designs. ACM Great Lakes Symposium on VLSI (2009)
Jin-Tai Yan, Zhi-Wei Chen
Timing-driven multi-layer Steiner tree construction with obstacle avoidance. APCCAS (2008)
Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee
Timing-constrained yield-driven redundant via insertion. APCCAS (2008)
Jin-Tai Yan, Zhi-Wei Chen
Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids. ICECS (2008)
Jin-Tai Yan, Zhi-Wei Chen, Yi-Hsiang Chou, Shun-Hua Lin, Herming Chiueh
Thermal-driven white space redistribution for block-level floorplans. ICECS (2008)
Jin-Tai Yan, Zhi-Wei Chen
Flexible escape routing for flip-chip designs. ICECS (2008)
Jin-Tai Yan, Zhi-Wei Chen
Electromigration-aware rectilinear Steiner tree construction for analog circuits. APCCAS (2008)
Jin-Tai Yan
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction. ACM Trans. Design Autom. Electr. Syst. 13 (2) (2008)
Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. ISCAS (2007)
Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity. SoCC (2007)
Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin
Routability-Driven Track Routing for Coupling Capacitance Reduction. ICECS (2007)
Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance. ICECS (2007)
Jin-Tai Yan, Bo-Yi Chiang
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. VLSI Design (2007)
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS (2006)
Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
Area-Driven White Space Distribution for Detailed Floorplan Design. ICECS (2006)
Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. ISCAS (2006)
Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. VLSI Design (2006)
Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang
Width and Timing-Constrained Wire Sizing for Critical Area Minimization. APCCAS (2006)
Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. ICECS (2006)
Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen
Optimal shielding insertion for inductive noise avoidance. ISCAS (2006)
Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee
Timing-constrained yield-driven wire sizing for critical area minimization. ISCAS (2006)
Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu
Optimal Network Analysis in Hierarchical Power Quad-Grids. APCCAS (2006)
Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. ISCAS (3) (2005)
Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen
Wiring area optimization in floorplan-aware hierarchical power grids. ISCAS (2) (2005)
Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee
Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. ISCAS (2) (2005)
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu
Probabilistic congestion prediction in hierarchical quad-grid model. ISCAS (2) (2005)
Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang
Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. ICECS (2005)
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee
Timing-Constrained Flexibility-Driven Routing Tree Construction. IEICE Trans. Inf. Syst. (7) (2005)
Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo
LB-packing-based floorplan design on DBL representation. ICECS (2005)
Jin-Tai Yan, Shun-Hua Lin
Timing-constrained congestion-driven global routing. ASP-DAC (2004)
Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen
Printed circuit board routing and package layout codesign. APCCAS (1) (2002)
Jin-Tai Yan
Three-layer bubble-sorting-based nonManhattan channel routing. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Jin-Tai Yan
An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement. VLSI Design 1999 (2) (1999)
Jin-Tai Yan
-type Junction Region. VLSI Design 1999 (2) (1999)
Jin-Tai Yan
An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jin-Tai Yan