Wang-Dauh Tseng

Publication Activity (10 Years)

Years Active: 1996-2021
Publications (10 Years): 4

Top Topics

Power Reduction

Data Compression

Top Venues

J. Inf. Sci. Eng.

J. Electron. Test.

Publications

Wang-Dauh Tseng
A Cascaded Multicasting Architecture for Test Data Compression. J. Electron. Test. 37 (2) (2021)
Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai
Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction. J. Inf. Sci. Eng. 35 (4) (2019)
Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai
Bipolar Dual-LFSR Reseeding for Low-Power Testing. DSC (2018)
Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai
Asymmetry dual-LFSR reseeding for low power BIST. Integr. 60 (2018)
Lung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang
Dual-LFSR Reseeding for Low Power Testing. MTV (2012)
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang
$2^{n}$ Pattern Run-Length for Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (4) (2012)
Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng
Deterministic ATPG for Low Capture Power Testing. MTV (2012)
Lung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen
Two-Way Multicasting for Test Data Compression. MTV (2012)
Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. IET Comput. Digit. Tech. 4 (4) (2010)
Wang-Dauh Tseng, Lung-Jen Lee
Test Data Compression Using Multi-dimensional Pattern Run-length Codes. J. Electron. Test. 26 (3) (2010)
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. Asian Test Symposium (2009)
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee
A Multi-dimensional Pattern Run-Length Method for Test Data Compression. Asian Test Symposium (2009)
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin
Power Reduction during Scan Testing Based on Multiple Capture Technique. IEICE Trans. Electron. (5) (2008)
Wang-Dauh Tseng
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing. J. Electron. Test. 23 (1) (2007)
I-Shyan Hwang, Ren-Yuan Cheng, Wang-Dauh Tseng
A novel dynamic Multiple Ring-based Local Restoration for point-to-multipoint multicast traffic in WDM mesh networks. Photonic Netw. Commun. 14 (1) (2007)
Wang-Dauh Tseng, Lung-Jen Lee
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering. MTV (2007)
I-Shyan Hwang, Meng-Yuan Tu, Wang-Dauh Tseng, Zen-Der Shyu
A novel dynamic fault restoration mechanism using cluster allocation approach in WDM mesh networks. Comput. Commun. 29 (18) (2006)
Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen
Printed circuit board routing and package layout codesign. APCCAS (1) (2002)
Wang-Dauh Tseng, Kuochen Wang
Fuzzy-based CMOS circuit partitioning in built-in current testing. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Wang-Dauh Tseng, Kuochen Wang
Fuzzy-based circuit partitioning in built-in current testing. ASP-DAC (1997)
Wang-Dauh Tseng, Kuochen Wang
Testable Design and Testing of MCMs Based on Multifrequency Scan. Asian Test Symposium (1996)