Routability-constrained multi-bit flip-flop construction for clock power reduction.

Zhi-Wei Chen Jin-Tai Yan

Published in: Integr. (2013)

Keyphrases

power dissipation
power consumption
power reduction
flip flops
clock gating
low power
power saving
high speed
cmos technology
energy efficiency
digital signal processing
multiple input
real time
data center
energy saving