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Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs.
Jin-Tai Yan
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
Keyphrases
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high speed
low power
printed circuit boards
high speed networks
real time
information retrieval
case study
multi layer
linear constraints
data sets
data mining
metadata
global constraints
design tools
constraint solving
constrained minimization