Low-power multiplier design with row and column bypassing.

Jin-Tai Yan Zhi-Wei Chen

Published in: SoCC (2009)

Keyphrases

low power
single chip
power consumption
low power consumption
low cost
high speed
vlsi architecture
gate array
logic circuits
digital signal processing
cmos technology
power dissipation
mixed signal
wireless transmission
high power
real time
design process
image processing