Adonios Thanailakis

Publication Activity (10 Years)

Years Active: 1986-2008
Publications (10 Years): 0

Publications

Vasilios A. Mardiris, Georgios Ch. Sirakoulis, Ch. Mizas, Ioannis Karafyllidis, Adonios Thanailakis
A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata. IEEE Trans. Syst. Man Cybern. Part C 38 (2) (2008)
Minas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis
A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2008)
Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis
Systematic methodology for designing low power direct digital frequency synthesisers. IET Circuits Devices Syst. 1 (4) (2007)
Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integr. 40 (2) (2007)
Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. Very Large Scale Integr. Syst. 14 (3) (2006)
Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis
A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS (2006)
Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS (2006)
N. A. Hastas, N. Archontas, C. A. Dimitriadis, G. Kamarinos, T. Nikolaidis, N. Georgoulas, Adonios Thanailakis
Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors. Microelectron. Reliab. 45 (2) (2005)
Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embed. Comput. 1 (3) (2005)
Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis
A cellular automaton for the propagation of circular fronts and its applications. Eng. Appl. Artif. Intell. 18 (6) (2005)
Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis
A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. J. Circuits Syst. Comput. 14 (2) (2005)
Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL (2005)
Nikolas Kroupis, Minas Dasygenis, Kleoniki Markou, Dimitrios Soudris, Adonios Thanailakis
A modified spiral search motion estimation algorithm and its embedded system implementation. ISCAS (4) (2005)
Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis
A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL (2005)
Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC (2005)
Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS (2005)
Georgios Ch. Sirakoulis, V. Raptis, Ioannis Karafyllidis, Philippos Tsalides, Adonios Thanailakis
A fault-tolerant message passing algorithm and its hardware implementation. Adv. Eng. Softw. 36 (3) (2005)
Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS (2004)
Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL (2004)
Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) (2003)
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL (2003)
Dimitrios Soudris, Marios Kesoulis, Christos S. Koukourlis, Adonios Thanailakis, Spyros Blionas
Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. ISCAS (2) (2003)
Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis
A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. Microprocess. Microsystems 27 (8) (2003)
Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Ch. Mizas, Vasilios A. Mardiris, Adonios Thanailakis, Philippos Tsalides
A cellular automaton model for the study of DNA sequence evolution. Comput. Biol. Medicine 33 (5) (2003)
Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis
FPGA Architecture Design and Toolset for Logic Implementation. PATMOS (2003)
Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis
Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC (2003)
Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS (2003)
S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
A fast and accurate delay dependent method for switching estimation of large combinational circuits. J. Syst. Archit. 48 (4-5) (2002)
Dimitrios Soudris, Minas Dasygenis, K. Mitroglou, Konstantinos Tatas, Adonios Thanailakis
A full adder based methodology for scaling operation in residue number system. ICECS (2002)
Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis
A cellular automaton methodology for the simulation of integrated circuit fabrication processes. Future Gener. Comput. Syst. 18 (5) (2002)
Konstantinos Tatas, D. J. Soudris, D. Siomos, Minas Dasygenis, Adonios Thanailakis
A novel division algorithm for parallel and sequential processing. ICECS (2002)
George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL (2002)
D. J. Soudris, Minas Dasygenis, Spyridoula K. Vasilopoulou, Adonios Thanailakis
A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) (2001)
Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis
The circuit design of multiple-valued logic voltage-mode adders. ISCAS (4) (2001)
Dimitrios Soudris, Vasilis F. Pavlidis, Adonios Thanailakis
Designing low-power energy recovery adders based on pass transistor logic. ICECS (2001)
Nikolaos D. Zervas, Dimitrios Soudris, Spyros Theoharis, Constantinos E. Goutis, Adonios Thanailakis
A methodology for the behavioral-level event-driven power management of digital receivers. ISCAS (2000)
D. J. Soudris, Minas Dasygenis, Adonios Thanailakis
Designing RNS and QRNS full adder based converters. ISCAS (2000)
Dimitrios Soudris, Minas Perakis, Haris Mizas, Vasilios A. Mardiris, Kosfas Katis, Chrissavgi Dre, A. E. Tzimas, E. G. Metaxakis, Grigorios Kalivas, Nikolaos D. Zervas, Spyros Theoharis, George Theodoridis, Adonios Thanailakis, Constantinos E. Goutis
Low power design of a multi-mode transceiver. ISCAS (2000)
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS (2000)
I. Thoidis, D. J. Soudris, Ioannis Karafyllidis, Adonios Thanailakis
The design of low power multiple-valued logic encoder and decoder circuits. ICECS (1999)
C. Z. Lolas, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis
A new adiabatic technique for designing low power array architectures. ICECS (1999)
M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, Grigorios A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis
The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) (1999)
George Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis
Genetic partitioning and placement for VLSI circuits. ICECS (1999)
Ioannis Karafyllidis, Stelios Mavridis, Dimitrios Soudris, Adonios Thanailakis
Estimation of power dissipation in glitching using complex-time cellular automata. ICECS (1999)
Ioannis Karafyllidis, Ioannis Andreadis, Philippos G. Tsalides, Adonios Thanailakis
Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems. VLSI Design 1998 (2) (1998)
I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. Great Lakes Symposium on VLSI (1998)
Panagiotis Tzionas, Adonios Thanailakis, Philippos G. Tsalides
An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. Image Vis. Comput. 15 (1) (1997)
Ioannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Philippos Tsalides
Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. Real Time Imaging 3 (4) (1997)
Panagiotis Tzionas, Adonios Thanailakis, Philippos G. Tsalides
Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automata. IEEE Trans. Robotics Autom. 13 (2) (1997)
Ioannis Andreadis, Ioannis Karafyllidis, Panagiotis Tzionas, Adonios Thanailakis, Philippos Tsalides
A new hardware module for automated visual inspection based on a cellular automaton architecture. J. Intell. Robotic Syst. 16 (1) (1996)
Ioannis Karafyllidis, Ioannis Andreadis, Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis
A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. Pattern Recognit. 29 (4) (1996)
Dimitrios Soudris, George Theodoridis, S. Theoharis, Adonios Thanailakis
Low-power design of array architectures. ICECS (1996)
Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis
A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. Real Time Imaging 1 (2) (1995)
Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Panagiotis Tzionas, Philippos Tsalides, Adonios Thanailakis
A modified discrete Fourier-cosine transform algorithm and its VLSI implementation. Microprocess. Microsystems 18 (6) (1994)
E. D. Adamides, Philippos G. Tsalides, Adonios Thanailakis
Bit-serial VLSI sorter with high reliability specifications. Microprocess. Microprogramming 40 (8) (1994)
Emmanuel D. Adamides, Philippos Tsalides, Adonios Thanailakis
Hierarchical Cellular Graph Automata as a Novel Architecture for Computer-Supported Cooperative Work. Comput. J. 35 (Additional-Papers) (1992)
E. D. Adamides, Philippos Tsalides, Adonios Thanailakis
Hierarchical Cellular Automata structures. Parallel Comput. 18 (5) (1992)
Philippos Tsalides, Adonios Thanailakis, Nikos Pitsianis, Georgios L. Bleris
Two-Dimensional Cellular Automata: Properties and Applications of a New VLSI Architecture. Comput. J. 35 (Additional-Papers) (1992)
Nikos Pitsianis, Georgios L. Bleris, Philippos Tsalides, Adonios Thanailakis, Howard C. Card
Algebraic Theory of Bounded One-dimensional Cellular Automata. Complex Syst. 3 (2) (1989)
E. D. Adamides, Philippos Tsalides, Adonios Thanailakis
Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. Parallel Comput. 11 (2) (1989)
Werner Pries, Adonios Thanailakis, Howard C. Card
Group Properties of Cellular Automata and VLSI Applications. IEEE Trans. Computers 35 (12) (1986)
Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod
Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. J. Comput. Syst. Sci. 33 (3) (1986)