D. J. Soudris

Publication Activity (10 Years)

Years Active: 1999-2005
Publications (10 Years): 0

Publications

Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL (2005)
Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. Microprocess. Microsystems 29 (6) (2005)
Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS (2004)
Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis
FPGA Architecture Design and Toolset for Logic Implementation. PATMOS (2003)
Konstantinos Tatas, D. J. Soudris, D. Siomos, Minas Dasygenis, Adonios Thanailakis
A novel division algorithm for parallel and sequential processing. ICECS (2002)
D. J. Soudris, Minas Dasygenis, Spyridoula K. Vasilopoulou, Adonios Thanailakis
A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) (2001)
D. J. Soudris, Minas Dasygenis, Adonios Thanailakis
Designing RNS and QRNS full adder based converters. ISCAS (2000)
I. Thoidis, D. J. Soudris, Ioannis Karafyllidis, Adonios Thanailakis
The design of low power multiple-valued logic encoder and decoder circuits. ICECS (1999)