George Theodoridis

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 15

Top Topics

Deblocking Filter

Reduced Complexity

Fpga Implementation

Top Venues

IET Comput. Digit. Tech.

Publications

Aimilios Leftheriotis, Aphrodite Tzomaka, Dimitrios Danopoulos, George Lentaris, George Theodoridis, Dimitrios Soudris
Evaluating Versal ACAP and conventional FPGA platforms for AI inference. MOCAST (2023)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. VLSI-SoC (2022)
Nikolaos Kefalas, George Theodoridis
An FPGA implementation of the VESA Display Stream Compression decoder. VLSI-SoC (2022)
S. Moraitis, D. Seitanidis, George Theodoridis, Odysseas G. Koufopavlou
Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers. VLSI-SOC (2020)
Nikolaos Kefalas, George Theodoridis
Implementing VESA Display Stream Compression Encoder in FPGAs. PATMOS (2019)
Nikolaos Kefalas, George Theodoridis
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard. Integr. 69 (2019)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. ACM Trans. Design Autom. Electr. Syst. 23 (2) (2018)
Nikolaos Kefalas, George Theodoridis
A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard. TSP (2018)
Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC (2018)
Nikolaos Kefalas, George Theodoridis
High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard. PATMOS (2017)
Andreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
Task graph mapping and scheduling on heterogeneous architectures under communication constraints. SAMOS (2017)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. ACM Trans. Embed. Comput. Syst. 15 (1) (2016)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
A hybrid approach for mapping and scheduling on heterogeneous multicore systems. SAMOS (2016)
Harris E. Michail, Georgios Athanasiou, George Theodoridis, Andreas Gregoriades, Costas E. Goutis
Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. Microprocess. Microsystems 45 (2016)
Harris E. Michail, George Athanasiou, Vasilios I. Kelefouras, George Theodoridis, Thanos Stouraitis, Costas E. Goutis
Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. J. Circuits Syst. Comput. 25 (4) (2016)
Andreas Emeretlis, V. Kefelouras, George Theodoridis, Maki Nanou, Christina Tanya Politi, Kristina Georgoulakis, George-Othon Glentis
FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. EUSIPCO (2015)
Nikolaos Kefalas, George Theodoridis
A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter. ICCE-Berlin (2015)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. ISVLSI (2015)
Maki Nanou, Andreas Emeretlis, Christina Tanya Politi, George Theodoridis, Kristina Georgoulakis, George-Othon Glentis
40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. ICTON (2015)
Nikolaos Kefalas, George Theodoridis
A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter. Integr. 49 (2015)
Andreas Emeretlis, George Theodoridis, George-Othon Glentis
High-performance FPGA implementations of volterra DFEs for optical fiber systems. ReConFig (2014)
Andreas Emeretlis, George Theodoridis
FPGA Implementations for Volterra DFEs. Panhellenic Conference on Informatics (2014)
Nikolaos Kefalas, George Theodoridis
An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC. ISCCSP (2014)
Georgios Athanasiou, Harris E. Michail, George Theodoridis, Costas E. Goutis
Optimising the SHA-512 cryptographic hash function on FPGAs. IET Comput. Digit. Tech. 8 (2) (2014)
Harris E. Michail, Georgios Athanasiou, George Theodoridis, Costas E. Goutis
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. Integr. 47 (4) (2014)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. IPDPS Workshops (2014)
George Athanasiou, Harris E. Michail, George Theodoridis, Costas E. Goutis
High-performance FPGA implementations of the cryptographic hash function JH. IET Comput. Digit. Tech. 7 (1) (2013)
George Athanasiou, George Theodoridis, Costas E. Goutis, Harris E. Michail, Takis Kasparis
A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. J. Circuits Syst. Comput. 22 (6) (2013)
Harris E. Michail, George Athanasiou, Andreas Gregoriades, George Theodoridis, Costas E. Goutis
On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. SECRYPT (2012)
Harris E. Michail, George Athanasiou, Vasilios I. Kelefouras, George Theodoridis, Costas E. Goutis
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC. ACM Trans. Reconfigurable Technol. Syst. 5 (1) (2012)
George Athanasiou, Chara I. Chalkou, D. Bardis, Harris E. Michail, George Theodoridis, Costas E. Goutis
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. SECRYPT (2012)
Nikolaos Kefalas, George Theodoridis
A high throughput pipelined architecture for H.264/AVC deblocking filter. ICECS (2010)
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
An Application Development Framework for ARISE Reconfigurable Processors. ACM Trans. Reconfigurable Technol. Syst. 2 (4) (2009)
George Theodoridis, Nikolaos Vassiliadis, Spiridon Nikolaidis
An integer linear programming model for mapping applications on hybrid systems. IET Comput. Digit. Tech. 3 (1) (2009)
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
ARISE Machines: Extending Processors with Hybrid Accelerators. ARC (2008)
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms CoRR (2007)
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
The ARISE Reconfigurable Instruction Set Extensions Framework. ICSAMOS (2007)
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. Microprocess. Microsystems 31 (1) (2007)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
A high-performance data path for synthesizing DSP kernels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. ARC (2006)
Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. J. Low Power Electron. 2 (3) (2006)
Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. J. Supercomput. 37 (2) (2006)
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
An automated development framework for a RISC processor with reconfigurable instruction set extensions. IPDPS (2006)
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A methodology for partitioning DSP applications in hybrid reconfigurable systems. ISCAS (2) (2005)
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. IPDPS (2005)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. J. Circuits Syst. Comput. 14 (4) (2005)
Nikolaos D. Zervas, George Theodoridis, Dimitrios Soudris
Behavioral-level event-driven power management for DECT digital receivers. Microelectron. J. 36 (2) (2005)
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Costas E. Goutis
A method for partitioning applications in hybrid reconfigurable architectures. Des. Autom. Embed. Syst. 10 (1) (2005)
Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis
A Novel Constant-Time Fault-Secure Binary Counter. PATMOS (2004)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS (2004)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. FPL (2004)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA (2004)
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE (2004)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
A high performance data-path to accelerate DSP kernels. ICECS (2004)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. FCCM (2004)
Athanasios Milidonis, Gregory Dimitroulakos, Michalis D. Galanis, Athanasios P. Kakarountas, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
A Framework for Data Partitioning for C++ Data-Intensive Applications. Des. Autom. Embed. Syst. 9 (2) (2004)
Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. SCOPES (2004)
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
A Novel Data-Path for Accelerating DSP Kernels. SAMOS (2004)
Paris Kitsos, George Theodoridis, Odysseas G. Koufopavlou
) for elliptic curve cryptosystem. ICECS (2003)
Athanasios P. Kakarountas, George Theodoridis, Kyriakos S. Papadomanolakis, Costas E. Goutis
A novel high-speed counter with counting rate independent of the counter's length. ICECS (2003)
Paris Kitsos, George Theodoridis, Odysseas G. Koufopavlou
). Microelectron. J. 34 (10) (2003)
Gregory Dimitroulakos, Athanasios Milidonis, Michalis D. Galanis, George Theodoridis, Costas E. Goutis, Francky Catthoor
Power aware data type refinement on the HIPERLAN/2. ICECS (2003)
S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
A fast and accurate delay dependent method for switching estimation of large combinational circuits. J. Syst. Archit. 48 (4-5) (2002)
George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. VLSI Design 2001 (1) (2001)
George Theodoridis, S. Theoharis, Dimitrios Soudris, Constantinos E. Goutis
A Fast and Accurate Method of Power Estimation for Logic Level Networks. VLSI Design 2001 (2) (2001)
Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. PATMOS (2000)
Dimitrios Soudris, Minas Perakis, Haris Mizas, Vasilios A. Mardiris, Kosfas Katis, Chrissavgi Dre, A. E. Tzimas, E. G. Metaxakis, Grigorios Kalivas, Nikolaos D. Zervas, Spyros Theoharis, George Theodoridis, Adonios Thanailakis, Constantinos E. Goutis
Low power design of a multi-mode transceiver. ISCAS (2000)
George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. PATMOS (2000)
George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis
A New Method for Low Power Design of Two-Level Logic Circuits. VLSI Design 1999 (2) (1999)
George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis
An efficient probabilistic method for logic circuits using real delay gate model. ISCAS (1) (1999)
George Theodoridis, S. Theoharis, Dimitrios Soudris, Odysseas G. Koufopavlou, Costas E. Goutis
A novel approach for reducing the switching activity in two-level logic circuits. ICECS (1996)
Dimitrios Soudris, George Theodoridis, S. Theoharis, Adonios Thanailakis
Low-power design of array architectures. ICECS (1996)