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FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links.
Andreas Emeretlis
V. Kefelouras
George Theodoridis
Maki Nanou
Christina Tanya Politi
Kristina Georgoulakis
George-Othon Glentis
Published in:
EUSIPCO (2015)
Keyphrases
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fpga implementation
hardware implementation
high speed
field programmable gate array
image processing
decision feedback
signal processing
communication systems
real time
neural network
computer vision
image analysis
software development
multiple input multiple output