Andreas Emeretlis

Publication Activity (10 Years)

Years Active: 2014-2022
Publications (10 Years): 5

Top Topics

Integer Linear Programming

Fpga Implementation

Benders Decomposition

Reduced Complexity

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. VLSI-SoC (2022)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. ACM Trans. Design Autom. Electr. Syst. 23 (2) (2018)
Andreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
Task graph mapping and scheduling on heterogeneous architectures under communication constraints. SAMOS (2017)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. ACM Trans. Embed. Comput. Syst. 15 (1) (2016)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
A hybrid approach for mapping and scheduling on heterogeneous multicore systems. SAMOS (2016)
Andreas Emeretlis, V. Kefelouras, George Theodoridis, Maki Nanou, Christina Tanya Politi, Kristina Georgoulakis, George-Othon Glentis
FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. EUSIPCO (2015)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. ISVLSI (2015)
Maki Nanou, Andreas Emeretlis, Christina Tanya Politi, George Theodoridis, Kristina Georgoulakis, George-Othon Glentis
40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. ICTON (2015)
Andreas Emeretlis, George Theodoridis, George-Othon Glentis
High-performance FPGA implementations of volterra DFEs for optical fiber systems. ReConFig (2014)
Andreas Emeretlis, George Theodoridis
FPGA Implementations for Volterra DFEs. Panhellenic Conference on Informatics (2014)
Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. IPDPS Workshops (2014)