An FPGA implementation of the VESA Display Stream Compression decoder.
Nikolaos KefalasGeorge TheodoridisPublished in: VLSI-SoC (2022)
Keyphrases
- fpga implementation
- hardware implementation
- real time
- data streams
- compression algorithm
- data compression
- image compression
- compression ratio
- compression scheme
- field programmable gate array
- pattern recognition
- image processing algorithms
- efficient implementation
- image coding
- wavelet transform
- video sequences
- information systems