Jens Sparsø

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 38

Top Topics

Noise Suppression

High Alpha Research Vehicle

Top Venues

J. Syst. Archit.

Publications

Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Riccardo Miccini, Alaa Zniber, Clément Laroche, Tobias Piechowiak, Martin Schoeberl, Luca Pezzarossa, Ouassim Karrakchou, Jens Sparsø, Mounir Ghogho
Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting. MLSP (2023)
Riccardo Miccini, Alaa Zniber, Clément Laroche, Tobias Piechowiak, Martin Schoeberl, Luca Pezzarossa, Ouassim Karrakchou, Jens Sparsø, Mounir Ghogho
Dynamic nsNet2: Efficient Deep Noise Suppression with Early Exiting. CoRR (2023)
Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø
A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks. ISCAS (2023)
Jens Sparsø, Hans Jakob Damsgaard, Dimitrios Katsamanis, Martin Schoeberl
Comparing timed-division multiplexing and best-effort networks-on-chip. J. Syst. Archit. 133 (2022)
Eleftherios Kyriakakis, Jens Sparsø, Martin Schoeberl
Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller. ETFA (2021)
Zuzana Jelcicová, Rasmus Jones, David Thorn Blix, Marian Verhelst, Jens Sparsø
PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks. EUSIPCO (2021)
Eleftherios Kyriakakis, Jens Sparsø, Peter P. Puschner, Martin Schoeberl
Synchronizing Real-Time Tasks in Time-Triggered Networks. ISORC (2021)
Zuzana Jelcicová, Adrian Mardari, Oskar Andersson, Evangelia Kasapaki, Jens Sparsø
A Neural Network Engine for Resource Constrained Embedded Systems. ACSSC (2020)
Eleftherios Kyriakakis, Jens Sparsø, Peter P. Puschner, Martin Schoeberl
Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress. EMSOFT (2020)
Eleftherios Kyriakakis, Maja Lund, Luca Pezzarossa, Jens Sparsø, Martin Schoeberl
A time-predictable open-source TTEthernet end-system. J. Syst. Archit. 108 (2020)
Adrian Mardari, Zuzana Jelcicová, Jens Sparsø
Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking. ASYNC (2019)
Martin Schoeberl, Luca Pezzarossa, Jens Sparsø
S4NOC: a minimalistic network-on-chip for real-time multicores. NoCArc@MICRO (2019)
Martin Schoeberl, Luca Pezzarossa, Jens Sparsø
A Minimal Network Interface for a Simple Network-on-Chip. ARCS (2019)
Martin Schoeberl, Tórur Biskopstø Strøm, Oktay Baris, Jens Sparsø
Scratchpad Memories with Ownership. DATE (2019)
Eleftherios Kyriakakis, Jens Sparsø, Martin Schoeberl
Implementing time-triggered communication over a standard ethernet switch. IoT-Fog@IoTDI (2019)
Oktay Baris, Shibarchi Majumder, Tórur Biskopstø Strøm, Anders la Cour-Harbo, Jens Sparsø, Thomas Bak, Martin Schoeberl
Demonstration of a Time-predictable Flight Controller on a Multicore Processor. ISORC (2019)
Tórur Biskopstø Strøm, Jens Sparsø, Martin Schoeberl
Hardlock: Real-time multicore locking. J. Syst. Archit. 97 (2019)
Maja Lund, Luca Pezzarossa, Jens Sparsø, Martin Schoeberl
A Time-predictable TTEthenet Node. ISORC (2019)
Eleftherios Kyriakakis, Jens Sparsø, Martin Schoeberl
Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol. RTNS (2018)
Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø
Using dynamic partial reconfiguration of FPGAs in real-Time systems. Microprocess. Microsystems 61 (2018)
Martin Schoeberl, Luca Pezzarossa, Jens Sparsø
A Multicore Processor for Time-Critical Applications. IEEE Des. Test 35 (2) (2018)
Jens Sparsø
Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016. Microprocess. Microsystems 60 (2018)
Rasmus Bo Sørensen, Luca Pezzarossa, Martin Schoeberl, Jens Sparsø
A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip. J. Syst. Archit. 74 (2017)
Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø
Can real-time systems benefit from dynamic partial reconfiguration? NORCAS (2017)
Martin Schoeberl, Jens Sparsø
Timing Organization of a Real-Time Multicore Processor. NGCAS (2017)
Luca Pezzarossa, Martin Schoeberl, Jens Sparsø
A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. ISORC (2017)
Andreas Toftegaard Kristensen, Luca Pezzarossa, Jens Sparsø
High-level synthesis for reduction of WCET in real-time systems. NORCAS (2017)
Luca Pezzarossa, Martin Schoeberl, Jens Sparsø
Reconfiguration in FPGA-based multi-core platforms for hard real-time applications. ReCoSoC (2016)
Evangelia Kasapaki, Martin Schoeberl, Rasmus Bo Sorensen, Christoph Thomas Muller, Kees Goossens, Jens Sparsø
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
André Rocha, Cláudio Silva, Rasmus Bo Sørensen, Jens Sparsø, Martin Schoeberl
Avionics Applications on a Time-Predictable Chip-Multiprocessor. PDP (2016)
Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø
State-based Communication on Time-predictable Multicore Processors. RTNS (2016)
Rasmus Bo Sorensen, Luca Pezzarossa, Jens Sparsø
An area-efficient TDM NoC supporting reconfiguration for mode changes. NOCS (2016)
Luca Pezzarossa, Rasmus Bo Sorensen, Martin Schoeberl, Jens Sparsø
Interfacing hardware accelerators to a time-division multiplexing network-on-chip. NORCAS (2015)
Rasmus Bo Sorensen, Wolfgang Puffitsch, Martin Schoeberl, Jens Sparsø
Message Passing on a Time-predictable Multicore Processor. ISORC (2015)
Martin Schoeberl, Sahar Abbaspour, Benny Akesson, Neil C. Audsley, Raffaele Capasso, Jamie Garside, Kees Goossens, Sven Goossens, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Alexander Jordan, Evangelia Kasapaki, Jens Knoop, Yonghui Li, Daniel Prokesch, Wolfgang Puffitsch, Peter P. Puschner, André Rocha, Cláudio Silva, Jens Sparsø, Alessandro Tocchi
T-CREST: Time-predictable multi-core architecture for embedded systems. J. Syst. Archit. 61 (9) (2015)
Martin Schoeberl, Rasmus Bo Sorensen, Jens Sparsø
Models of Communication for Multicore Processors. ISORC Workshops (2015)
Evangelia Kasapaki, Jens Sparsø
The Argo NOC: Combining TDM and GALS. ECCTD (2015)
Rasmus Bo Sorensen, Jens Sparsø, Mark Ruvald Pedersen, Jaspur Hojgaard
A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip. ISORC (2014)
Christoph Thomas Muller, Evangelia Kasapaki, Rasmus Bo Sorensen, Jens Sparsø
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools. NORCHIP (2014)
I. Kotleas, D. Humphreys, Rasmus Bo Sorensen, Evangelia Kasapaki, Florian Brandner, Jens Sparsø
A loosely synchronizing asynchronous router for TDM-scheduled NOCs. NOCS (2014)
Mathias Herlev, Christian Keis Poulsen, Jens Sparsø
Open core protocol (OCP) clock domain crossing interfaces. NORCHIP (2014)
Martin Schoeberl, David Vh Chong, Wolfgang Puffitsch, Jens Sparsø
A Time-Predictable Memory Network-on-Chip. WCET (2014)
Evangelia Kasapaki, Jens Sparsø
Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers. ASYNC (2014)
Evangelia Kasapaki, Jens Sparsø, Rasmus Bo Sorensen, Kees Goossens
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip. DSD (2013)
Jens Sparsø, Evangelia Kasapaki, Martin Schoeberl
An area-efficient network interface for a TDM-based network-on-chip. DATE (2013)
Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. VLSI-SoC (2013)
Jens Sparsø
Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip. ACSD (2012)
Rasmus Bo Sorensen, Martin Schoeberl, Jens Sparsø
A light-weight statically scheduled network-on-chip. NORCHIP (2012)
Martin Schoeberl, Florian Brandner, Jens Sparsø, Evangelia Kasapaki
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems. NOCS (2012)
Matthias Bo Stuart, Jens Sparsø
Analytical derivation of traffic patterns in cache-coherent shared-memory systems. Microprocess. Microsystems 35 (7) (2011)
Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø
Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection. IET Comput. Digit. Tech. 5 (4) (2011)
Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation. ACM Trans. Embed. Comput. Syst. 10 (4) (2011)
Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø
Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study. ASYNC (2010)
Sune Fallgaard Nielsen, Jens Sparsø, Jan Madsen
Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Sune Fallgaard Nielsen, Jens Sparsø, Jonas Braband Jensen, Johan Sebastian Rosenkilde Nielsen
A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow. ASYNC (2009)
Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø
Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. CODES+ISSS (2009)
Jens Sparsø
Current trends in high-level synthesis of asynchronous circuits. ICECS (2009)
Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
A Reactive and Cycle-True IP Emulator for MPSoC Exploration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Mikkel Bystrup Stensgaard, Jens Sparsø
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. NOCS (2008)
Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. DATE (2007)
Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. DSD (2006)
Tobias Bjerregaard, Jens Sparsø
Packetizing OCP Transactions in the MANGO Network-on-Chip. DSD (2006)
Tobias Bjerregaard, Jens Sparsø
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. DATE (2005)
Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen
A Network Traffic Generator Model for Fast Network-on-Chip Simulation. DATE (2005)
Tobias Bjerregaard, Jens Sparsø
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. ASYNC (2005)
Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. SoC (2005)
Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
A Traffic Injection Methodology with Support for System-Level Synchronization. VLSI-SoC (2005)
Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. PATMOS (2004)
Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. J. VLSI Signal Process. 37 (1) (2004)
Sune Fallgaard Nielsen, Jens Sparsø, Jan Madsen
Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. DSD (2004)
Vojin G. Oklobdzija, Jens Sparsø
Future directions in clocking multi-ghz systems. ISLPED (2002)
Lars Skovby Nielsen, Jens Sparsø
Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid. Proc. IEEE 87 (2) (1999)
Kåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. ASYNC (1998)
Lars Skovby Nielsen, Jens Sparsø
A low-power asynchronous data-path for a FIR filter bank. ASYNC (1996)
Lars Skovby Nielsen, Cees Niessen, Jens Sparsø, Kees van Berkel
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)
Jens Sparsø, Jørgen Staunstrup
Delay-insensitive multi-ring structures. Integr. 15 (3) (1993)
Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup
Design of Self-timed Multipliers: A Comparison. Asynchronous Design Methodologies (1993)
Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen
Design of delay insensitive circuits using multi-ring structures. EURO-DAC (1992)
Erik Paaske, Steen Pedersen, Jens Sparsø
An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders. Integr. 12 (1) (1991)
Jens Sparsø, Steen Pedersen, Erik Paaske
Design of a Fully Parallel Viterbi Decoder. VLSI (1991)