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A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs.
Christoph Thomas Muller
Steffen Malkowsky
Oskar Andersson
Babak Mohammadi
Jens Sparsø
Joachim Neves Rodrigues
Published in:
VLSI-SoC (2013)
Keyphrases
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nm technology
silicon on insulator
power consumption
low power
cmos technology
flow patterns
high speed
power dissipation
low cost
image processing
multi stream
analog vlsi
ibm power processor
metal oxide semiconductor
flow field
circuit design
power management
potential functions
image processing algorithms