David Esseni

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 14

Top Topics

Spiking Neurons

Surface Roughness

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

David Esseni, Francesco Driussi, Daniel Lizzit, Marco Massarotto, Mattia Segatto
Modelling and Simulations of Ferroelectric Materials and Ferroelectric-Based Nanoelectronic Devices. CoRR (2023)
Suzanne Lancaster, Mattia Segatto, Cláudia Silva, Benjamin Max, Thomas Mikolajick, David Esseni, Francesco Driussi, Stefan Slesazeck
Reducing the tunneling barrier thickness of bilayer ferroelectric tunnel junctions with metallic electrodes. DRC (2023)
Marco Massarotto, S. Saggini, Mirko Loghi, David Esseni
Adiabatic Spiking Neurons and Synapses for Ultra-Low Energy Neuromorphic Computing. ICECS (2023)
Daniel Lizzit, Thomas Bernardi, David Esseni
Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects. CoRR (2023)
Riccardo Fontanini, David Esseni, Mirko Loghi
Reducing the Spike Rate in Deep Spiking Neural Networks. ICONS (2022)
Mattia Segatto, Marco Massarotto, Suzanne Lancaster, Quang T. Duong, A. Affanni, Riccardo Fontanini, Francesco Driussi, Daniel Lizzit, Thomas Mikolajick, Stefan Slesazeck, David Esseni
Polarization switching and AC small-signal capacitance in Ferroelectric Tunnel Junctions. ESSDERC (2022)
Daniel Lizzit, David Esseni
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation. CoRR (2022)
Daniel Lizzit, Thomas Bernardi, David Esseni
Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects. ESSDERC (2022)
Riccardo Fontanini, Marco Massarotto, Ruben Specogna, Francesco Driussi, Mirko Loghi, David Esseni
Modelling and design of FTJs as high reading-impedance synaptic devices. CoRR (2021)
David Esseni, Riccardo Fontanini, Daniel Lizzit, Marco Massarotto, Francesco Driussi, Mirko Loghi
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies. CoRR (2021)
Daniel Lizzit, David Esseni
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation. ESSDERC (2021)
Riccardo Fontanini, Justine Barbot, M. Segatto, Suzanne Lancaster, Quang T. Duong, Francesco Driussi, Laurent Grenouillet, Francois Triozon, Jean Coignus, Thomas Mikolajick, Stefan Slesazeck, David Esseni
Polarization switching and interface charges in BEOL compatible Ferroelectric Tunnel Junctions. ESSDERC (2021)
Martin Rau, Troels Markussen, Enrico Caruso, David Esseni, Elena Gnani, Antonio Gnudi, Petr A. Khomyakov, Mathieu Luisier, Patrik Osgnach, Pierpaolo Palestri, Susanna Reggiani, Andreas Schenk, Luca Selmi, Kurt Stokbro
Performance study of strained III-V materials for ultra-thin body transistor applications. ESSDERC (2016)
Tommaso Rollo, David Esseni
Supersteep retrograde doping in ferroelectric MOSFETs for sub-60mV/dec subthreshold swing. ESSDERC (2016)
Pierpaolo Palestri, Enrico Caruso, Francesco Driussi, David Esseni, Daniel Lizzit, Patrik Osgnach, Stefano Venica, Luca Selmi
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors. MIPRO (2015)
O. Badami, Enrico Caruso, Daniel Lizzit, David Esseni, Pierpaolo Palestri, Luca Selmi
Improved surface roughness modeling and mobility projections in thin film MOSFETs. ESSDERC (2015)
Manouchehr Hosseini, Mohammad Elahi, Ebrahim Asl Soleimani, Mahdi Pourfath, David Esseni
Strain engineering of single-layer MoS2. ESSDERC (2015)
Sebastiano Strangio, Pierpaolo Palestri, David Esseni, Luca Selmi, Felice Crupi
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. ESSDERC (2014)
Massimo Alioto, David Esseni
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits. SBCCI (2014)
David Esseni, Massimo Alioto
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits. NEWCAS (2014)
Massimo Alioto, David Esseni
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
Daniel Lizzit, Pierpaolo Palestri, David Esseni, Francesco Conzatti, Luca Selmi
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs. ESSDERC (2012)
Davide Baccarin, David Esseni, Massimo Alioto
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Davide Baccarin, David Esseni, Massimo Alioto
A novel back-biasing low-leakage technique for FinFET forced stacks. ISCAS (2011)
Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Michele Nocente, Donald Fontanelli, Pierpaolo Palestri, Roberto Nonis, David Esseni, Luca Selmi
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. Int. J. Circuit Theory Appl. 38 (6) (2010)
Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Domagoj Siprak, Gerhard Knoblinger
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2009)
Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. PATMOS (2008)
Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Gerhard Knoblinger
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET. ISCAS (2008)
Enrico Sangiorgi, Pierpaolo Palestri, David Esseni, Claudio Fiegna, Luca Selmi
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs. ESSCIRC (2007)
Roberto Versari, David Esseni, Gianluca Falavigna, Massimo Lanzoni, Bruno Riccò
Optimized programming of multilevel flash EEPROMs. ICECS (2001)