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Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.
Massimo Alioto
David Esseni
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2014)
Keyphrases
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mixed signal
vlsi circuits
low voltage
low power
cmos technology
high speed
multi channel
digital circuits
design considerations
circuit design
digital signal processing
power line
power dissipation
parallel processing
power consumption
phase locked loop
power management
digital images