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Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.

Matteo AgostinelliMassimo AliotoDavid EsseniLuca Selmi
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
  • logic circuits
  • gate array
  • low power
  • power dissipation
  • power consumption
  • functional decomposition
  • logic synthesis
  • case study
  • computational complexity
  • computer systems
  • wireless networks
  • tunnel diode
  • high speed