Ching-Che Chung

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 20

Top Topics

Fault Diagnosis

Aerial Vehicles

Convolutional Codes

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Microelectron. J.

Publications

Yu-Pei Liang, Chen-Ming Chang, Ching-Che Chung
Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles. Sensors 24 (7) (2024)
Yu-Pei Liang, Yao-Shun Hsu, Ching-Che Chung
A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis. IEEE Trans. Instrum. Meas. 73 (2024)
Ching-Che Chung, Yu-Pei Liang, Hong-Jin Jiang
CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis. Sensors 23 (13) (2023)
Ching-Che Chung, Yu-Pei Liang, Jo-Chen Huang
Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery. ICCE-Taiwan (2023)
Yu-Pei Liang, Ming-You Hung, Ching-Che Chung
A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery. Sensors 23 (23) (2023)
Tsung-Hsien Liu, Ting-Xu Jiang, Ching-Che Chung, Yuan-Sun Chu
A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (9) (2022)
Ching-Che Chung, Yi-Ting Tsai
A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. VLSI-DAT (2022)
Ching-Che Chung, Huai-Xiang Zhang, Ming-You Hung, Hong-Jin Jian
A DBN Hardware Accelerator for Auditory Scene Classification. ICCE-TW (2020)
Ching-Che Chung, Duo Sheng, Ming-Hsuan Li
Design of a human body channel communication transceiver using convolutional codes. Microelectron. J. 100 (2020)
Ching-Che Chung, Yi-Zeng Lee, Huai-Xiang Zhang
Design of a DBN Hardware Accelerator for Handwritten Digit Recognitions. ICCE-TW (2019)
Ching-Che Chung, Wei-Jung Chu, Yi-Ting Tsai
Built-in Self-Test Circuits for All-digital Phase-Locked Loops. ICCE-TW (2019)
Ching-Che Chung, Hsin-Han Huang
An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications. SoCC (2019)
Ching-Che Chung, Duo Sheng, Ming-Chieh Li, Yi-Che Tsai
A fast phase tracking reference-less all-digital CDR circuit for human body channel communication. Microelectron. J. 84 (2019)
Ching-Che Chung, Chi-Yu Hou
An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. Microelectron. J. 70 (2017)
Ching-Che Chung, Yi-Che Tsai, Ming-Chieh Li
A reference-less all-digital transceiver for human body channel communication. VLSI-DAT (2017)
Ching-Che Chung, Jhih-Wei Li
A cell-based 5-MHz on-chip clock generator. Turkish J. Electr. Eng. Comput. Sci. 25 (2017)
Ching-Che Chung, Chien-Ying Yu
An area-efficient and wide-range digital DLL for per-pin deskew applications. Turkish J. Electr. Eng. Comput. Sci. 25 (2017)
Ching-Che Chung, Wei-Siang Su, Chi-Kuang Lo
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Ching-Che Chung, Mei-I Sun
An all-digital voltage sensor for static voltage drop measurements. SAS (2016)
Ching-Che Chung, Chi-Kuang Lo
A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology. IEICE Electron. Express 13 (17) (2016)
Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin
A 1 Mb/s-40 Mb/s human body channel communication transceiver. VLSI-DAT (2015)
Ching-Che Chung, Duo Sheng, Chang-Jun Li
A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Ching-Che Chung, Duo Sheng, Wei-Da Ho
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Ching-Che Chung, Jhih-Wei Li
An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management. SoCC (2014)
Ching-Che Chung, Chi-Yu Hou
All-digital delay-locked loop for 3D-IC die-to-die clock synchronization. VLSI-DAT (2014)
Ching-Che Chung, Duo Sheng, Chen-Han Chen
An all-digital phase-locked loop compiler with liberty timing files. VLSI-DAT (2014)
Ching-Che Chung, Hao-Hsiang Hsu
Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Ching-Che Chung, Duo Sheng, Sung-En Shen
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, Shu-Syun Jhao
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications. IEICE Electron. Express 11 (3) (2014)
Duo Sheng, Ching-Che Chung, Chih-Chung Huang, Jia-Wei Jian
A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications. EMBC (2013)
Ching-Che Chung, Chang-Jun Li
A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. VLSI-DAT (2013)
Ching-Che Chung, Duo Sheng, Wei-Da Ho
A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS. IEICE Electron. Express 10 (6) (2013)
Ching-Che Chung, Duo Sheng, Wei-Siang Su
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. VLSI-DAT (2013)
Ching-Che Chung, Jhih-Wei Li
An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling. ISCAS (2013)
Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee
A Low-Power DCO Using Interlaced Hysteresis Delay Cells. IEEE Trans. Circuits Syst. II Express Briefs (10) (2012)
Ching-Che Chung, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, Fang-Nien Lu
An All-Digital Large-N Audio Frequency Synthesizer for HDMI Applications. IEEE Trans. Circuits Syst. II Express Briefs (7) (2012)
Ching-Che Chung, Duo Sheng, Ning-Mi Hsueh
A high-performance wear-leveling algorithm for flash memory system. IEICE Electron. Express 9 (24) (2012)
Ching-Che Chung, Ning-Mi Hsueh
A low-complexity high-performance wear-leveling algorithm for flash memory system design. APCCAS (2012)
Ching-Che Chung, Duo Sheng, Wei-Da Ho
A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology. VLSI-DAT (2012)
Ching-Che Chung, Duo Sheng, Sung-En Shen
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology. IEICE Electron. Express 8 (15) (2011)
Ching-Che Chung, Chiun-Yao Ko, Sung-En Shen
Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (3) (2011)
Ching-Che Chung, Cheng-Ruei Yang
An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring. IEEE Trans. Circuits Syst. II Express Briefs (2) (2011)
Ching-Che Chung, Duo Sheng, Chia-Lin Chang
A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. IEICE Electron. Express 8 (7) (2011)
Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, Chen-Yi Lee
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. J. Signal Process. Syst. 64 (2) (2011)
Ching-Che Chung, Chiun-Yao Ko
A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology. IEEE J. Solid State Circuits 46 (10) (2011)
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Ching-Che Chung, Cheng-Ruei Yang
An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology. ISCAS (2010)
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. IEICE Electron. Express 7 (9) (2010)
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. APCCAS (2008)
Jui-Yuan Yu, Ching-Che Chung, Chen-Yi Lee
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. IEEE Trans. Circuits Syst. II Express Briefs (9) (2008)
Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. ISSCC (2007)
Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. SoCC (2007)
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. IEEE Trans. Circuits Syst. II Express Briefs (11) (2007)
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. APCCAS (2006)
Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE J. Solid State Circuits 41 (6) (2006)
Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. DAC (2006)
Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
A portable digitally controlled oscillator using novel varactors. IEEE Trans. Circuits Syst. II Express Briefs (5) (2005)
Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) (2005)
Ching-Che Chung, Chen-Yi Lee
A new DLL-based approach for all-digital multiphase clock generation. IEEE J. Solid State Circuits 39 (3) (2004)
Ching-Che Chung, Chen-Yi Lee
An all-digital phase-locked loop for high-speed clock generation. IEEE J. Solid State Circuits 38 (2) (2003)