A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology.

Ching-Che Chung Chi-Kuang Lo

Published in: IEICE Electron. Express (2016)

Keyphrases

cmos technology
phase locked loop
low power
mixed signal
spl times
parallel processing
low voltage
power consumption
high voltage
image sensor
high speed
multipath
silicon on insulator
low cost
cmos image sensor
dynamic range
power dissipation
real time
computer systems
control system
image processing