A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology.
Ching-Che ChungDuo ShengChia-Lin ChangPublished in: IEICE Electron. Express (2011)
Keyphrases
- cmos technology
- mixed signal
- clock frequency
- power dissipation
- low power
- power consumption
- spl times
- high speed
- low voltage
- parallel processing
- cmos image sensor
- image sensor
- silicon on insulator
- low cost
- neural network
- image analysis
- digital signal processing
- finite state machines
- hardware and software
- video sequences