A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.
Duo ShengChing-Che ChungChen-Yi LeePublished in: APCCAS (2006)
Keyphrases
- low power
- high resolution
- user friendly
- high speed
- low cost
- power consumption
- phase locked loop
- super resolution
- single chip
- image processing
- high frequency
- low power consumption
- high power
- wireless transmission
- vlsi circuits
- logic circuits
- gate array
- high quality
- vlsi architecture
- cmos technology
- digital signal processing
- power reduction
- error correction
- embedded systems
- wireless networks