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All-digital delay-locked loop for 3D-IC die-to-die clock synchronization.

Ching-Che ChungChi-Yu Hou
Published in: VLSI-DAT (2014)
Keyphrases
  • phase locked loop
  • neural network
  • high speed
  • integrated circuit
  • data sets
  • data mining
  • image sequences
  • end to end
  • multipath