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A Low-Power DCO Using Interlaced Hysteresis Delay Cells.
Chien-Ying Yu
Ching-Che Chung
Chia-Jung Yu
Chen-Yi Lee
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2012)
Keyphrases
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low power
power dissipation
high speed
power consumption
low cost
digital signal processing
high power
single chip
motion compensation
image sensor
wireless transmission
motion compensated
vlsi circuits
logic circuits
vlsi architecture
low power consumption
power reduction
cmos technology