Yizheng Ye

Publication Activity (10 Years)

Years Active: 1998-2012
Publications (10 Years): 0

Top Topics

Distributed Architecture

Top Venues

J. Low Power Electron.

Publications

Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao
Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost. J. Low Power Electron. 8 (1) (2012)
Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping. J. Electron. Test. 27 (1) (2011)
Bin Zhou, Yizheng Ye, Zhao-lin Li, Jianwei Zhang, Xin-chun Wu, Rui Ke
A test set embedding approach based on twisted-ring counter with few seeds. Integr. 43 (1) (2010)
Zhibo Zhou, Jinxiang Wang, Yizheng Ye
Exact BER Analysis of Differential Chaos Shift Keying Communication System in Fading Channels. Wirel. Pers. Commun. 53 (2) (2010)
Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke
A new low power test pattern generator using a variable-length ring counter. ISQED (2009)
Bin Zhou, Yizheng Ye, Xin-chun Wu, Zhao-lin Li
Reduction of Test Power and Data Volume in BIST Scheme based on Scan Slice Overlapping. ISCAS (2009)
Jianwei Zhang, Yizheng Ye, Bin-Da Liu, Feng Guan
Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories. ISCAS (2009)
Jianwei Zhang, Yizheng Ye, Bin-Da Liu
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye
A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-Ends. IEEE Trans. Circuits Syst. II Express Briefs (8) (2008)
Qingli Zhang, Jinxiang Wang, Yizheng Ye
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. VLSI Design (2008)
Bin Zhou, Yizheng Ye, Yongsheng Wang
Simultaneous reduction in test data volume and test time for TRC-reseeding. ACM Great Lakes Symposium on VLSI (2007)
Tong Zhou, Zhibo Zhou, Mingyan Yu, Yizheng Ye
Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator. APCCAS (2006)
Jianwei Zhang, Yizheng Ye, Bin-Da Liu
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. ISLPED (2006)
Qingli Zhang, Jinxiang Wang, Yizheng Ye
An energy-efficient temporal encoding circuit technique for on-chip high performance buses. ACM Great Lakes Symposium on VLSI (2006)
Qingli Zhang, Jinxiang Wang, Yizheng Ye
Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. APCCAS (2006)
Jianwei Zhang, Yizheng Ye, Bin-Da Liu
A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories. APCCAS (2006)
Zhiqiang Gao, Mingyan Yu, Yizheng Ye, Jianguo Ma
A CMOS bandpass filter with wide-tuning range for wireless applications. ISCAS (2006)
Guochi Huang, Tae-Sung Kim, Byung-Sung Kim, Mingyan Yu, Yizheng Ye
Post linearization of CMOS LNA using double cascade FETs. ISCAS (2006)
Shengtian Sang, Xiaoming Li, Yizheng Ye
Dependency driven partitioning objects generation for hardware/software partitioning. ISCAS (2006)
Tong Zhou, Mingyan Yu, Yizheng Ye
A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor. VLSI Design (2006)
Yongsheng Wang, Jinxiang Wang, Fengchang Lai, Yizheng Ye
Optimal Schemes for ADC BIST Based on Histogram. Asian Test Symposium (2005)
Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye
A CMOS RF tuning wide-band bandpass filter for wireless applications. SoCC (2005)
Zhiqiang Gao, Jianguo Ma, Yizheng Ye, Mingyan Yu
Large tuning band range of high frequency filter for wireless applications. ISCAS (1) (2005)
Zhonghai Wang, Yizheng Ye
The improvement for transaction level verification functional coverage. ISCAS (6) (2005)
Yongsheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye
A Test Architecture for System-on-a-Chip. Asian Test Symposium (2003)
Liyi Xiao, Yizheng Ye, Bin Li
A New Synchronization Algorithm for VHDL-AMS Simulation. J. Comput. Sci. Technol. 17 (1) (2002)
Xuemei Zhao, Yizheng Ye
Design and Realization of a Low Power Register File Using Energy Model. PATMOS (2002)
Yuxin You, Jinxiang Wang, Mingyan Yu, Yizheng Ye
Design and implementation of concatenated decoder. DCV (2002)
Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang
A mixed-signal simulator for VHDL-AMS. ASP-DAC (2001)
Bin Li, Liyi Xiao, Yizheng Ye, Guoyong Huang
CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit Simulation. Annual Simulation Symposium (2001)
Liu Songyan, Zhigang Mao, Yizheng Ye
Implementation of Java Card Virtual Machine. J. Comput. Sci. Technol. 15 (6) (2000)
Zulan Huang, Yizheng Ye, Zhigang Mao
A New Algorithm for Retiming-Based Partial Scan. Asian Test Symposium (1999)
Pingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng
Test Pattern Generation for Column Compression Multiplier. Asian Test Symposium (1998)