Xiangsheng Fang

Publication Activity (10 Years)

Years Active: 2005-2019
Publications (10 Years): 7

Top Topics

Cmos Technology

Design Methodology

Low Power Consumption

Top Venues

IEICE Electron. Express

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang, Jie Cui, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Tai Song, Huaguo Liang, Ying Sun, Zhengfeng Huang, Maoxiang Yi, Xiangsheng Fang, Aibin Yan
Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory. VTS (2019)
Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique. ITC-Asia (2018)
Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen
Vernier ring based pre-bond through silicon vias test in 3D ICs. IEICE Electron. Express 14 (18) (2017)
Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Yiming Ouyang, Honghui Deng
Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS. Microelectron. J. 61 (2017)
Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi
A highly reliable butterfly PUF in SRAM-based FPGAs. IEICE Electron. Express 14 (14) (2017)
Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang
Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. ATS (2016)
Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang
A BIST Scheme Based on Selecting State Generation of Folding Counters. Asian Test Symposium (2005)