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Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.

Aibin YanZhengfeng HuangXiangsheng FangXiaolin XuHuaguo Liang
Published in: ATS (2016)
Keyphrases
  • low power
  • low cost
  • cmos technology
  • power consumption
  • single chip
  • low power consumption
  • mixed signal
  • power dissipation
  • digital signal processing
  • real time
  • case study
  • embedded systems