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Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.

Aibin YanZhengfeng HuangXiangsheng FangYiming OuyangHonghui Deng
Published in: Microelectron. J. (2017)
Keyphrases
  • power consumption
  • case study
  • high speed
  • low power
  • steady state
  • neural network
  • markov chain
  • embedded systems
  • engineering design
  • design methodology
  • single chip
  • power reduction