A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
Aibin YanKang YangZhengfeng HuangJiliang ZhangJie CuiXiangsheng FangMaoxiang YiXiaoqing WenPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
- low power
- low power consumption
- power consumption
- single chip
- ultra low power
- low cost
- high speed
- vlsi architecture
- digital signal processing
- logic circuits
- power dissipation
- power reduction
- gate array
- cmos technology
- high power
- wireless transmission
- signal processor
- mixed signal
- application specific
- vlsi circuits
- design process
- nm technology
- embedded systems
- hardware and software