Pieter De Wit

Publication Activity (10 Years)

Years Active: 2008-2012
Publications (10 Years): 0

Top Topics

Design Principles

Wavelet Packet Transform

Fault Diagnosis

Analog Circuits

Top Venues

IEEE J. Solid State Circuits

Publications

Pieter De Wit, Georges G. E. Gielen
Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS. IEEE J. Solid State Circuits 47 (7) (2012)
Swaraj Mahato, Pieter De Wit, Elie Maricau, Georges G. E. Gielen
Offset measurement method for accurate characterization of BTI-induced degradation in opamps. ICECS (2012)
Georges G. E. Gielen, Elie Maricau, Pieter De Wit
Designing reliable analog circuits in an unreliable world. CICC (2012)
Pieter De Wit, Georges G. E. Gielen
A failure-resilient xDSL line driver with on-chip degradation monitor. ESSCIRC (2011)
Simon Vanden Bussche, Pieter De Wit, Elie Maricau, Georges G. E. Gielen
Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS. ICECS (2011)
Georges G. E. Gielen, Elie Maricau, Pieter De Wit
Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation. DATE (2011)
Pieter De Wit, Georges G. E. Gielen
Efficient simulation model for DAC dynamic properties. ISCAS (2010)
Georges G. E. Gielen, Elie Maricau, Pieter De Wit
Design automation towards reliable analog integrated circuits. ICCAD (2010)
Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel S. J. Steyaert
A 66 µW 86 ppm° C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM. IEEE J. Solid State Circuits 44 (7) (2009)
Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel Steyaert
Erratum to "A 66 µW 86 ppm°C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM" [Jul 09 1990-2001]. IEEE J. Solid State Circuits 44 (10) (2009)
Elie Maricau, Pieter De Wit, Georges G. E. Gielen
An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications. Microelectron. Reliab. 48 (8-9) (2008)
Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel Steyaert
A fully-integrated Wienbridge topology for ultra-low-power 86ppm/°C 65nm CMOS 6MHz clock reference with amplitude regulation. ESSCIRC (2008)
Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. DATE (2008)