A failure-resilient xDSL line driver with on-chip degradation monitor.

Pieter De Wit Georges G. E. Gielen

Published in: ESSCIRC (2011)

Keyphrases

real time
high speed
low cost
high density
vlsi design
line segments
monitoring system
chip design
cmos technology
single chip
neural network
image sensor
root cause
high bandwidth
hough transform
vlsi implementation
failure detection
database