Klaas Bult

Publication Activity (10 Years)

Years Active: 1997-2020
Publications (10 Years): 5

Top Topics

Design Considerations

Top Venues

IEEE J. Solid State Circuits

Publications

Md Shakil Akter, Rohan Sehgal, Klaas Bult
A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers. IEEE Trans. Circuits Syst. (11) (2020)
Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Kofi A. A. Makinwa, Klaas Bult
A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier. IEEE J. Solid State Circuits 53 (10) (2018)
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers. IEEE J. Solid State Circuits 53 (7) (2018)
Md Shakil Akter, Kofi A. A. Makinwa, Klaas Bult
A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier. IEEE J. Solid State Circuits 53 (4) (2018)
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers. ESSCIRC (2017)
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. IEEE J. Solid State Circuits 50 (7) (2015)
Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. ISSCC (2015)
Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. ESSCIRC (2015)
Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. ISSCC (2014)
Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. CICC (2014)
Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid State Circuits 49 (12) (2014)
Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. ISSCC (2014)
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. ESSCIRC (2014)
Silvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS. IEEE J. Solid State Circuits 48 (7) (2013)
Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. IEEE J. Solid State Circuits 46 (12) (2011)
Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC (2011)
Klaas Bult
Embedded analog-to-digital converters. ESSCIRC (2009)
Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. ISSCC (2009)
Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 44 (12) (2009)
Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes
0.13-μm CMOS. IEEE J. Solid State Circuits 39 (12) (2004)
Alan Y. Kwentus, Patrick Pai, Steven Jaffe, Ray Gomez, Shauhyuarn Sean Tsai, Tom Kwan, Hing T. Hung, Young J. Shin, Vin Hue, Darwin Cheung, Raheel A. Khan, Christopher M. Ward, Mong-Kai Ku, Kenneth Choi, Jim Searle, Klaas Bult, Kelly Cameron, Jason Demas, Charles Reames, Henry Samueli
A single-chip universal digital satellite receiver with 480-MHz IF input. IEEE J. Solid State Circuits 34 (11) (1999)
Mehdi Hatamian, Oscar E. Agazzi, John Creigh, Henry Samueli, Andrew J. Castellano, David Kruse, Avi Madisetti, Nariman Yousefi, Klaas Bult, Patrick Pai, Myles Wakayama, Mike M. McConnell, Marty Colombatt
Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers. CICC (1998)
Chi-Hung Lin, Klaas Bult
. IEEE J. Solid State Circuits 33 (12) (1998)
Klaas Bult, Aaron Buchwald
. IEEE J. Solid State Circuits 32 (11) (1997)