A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.
Frank M. L. van der GoesChristopher M. WardSantosh AstgimathHan YanJeff RileyZeng ZengJan MulderSijia WangKlaas BultPublished in: IEEE J. Solid State Circuits (2014)
Keyphrases
- power consumption
- nm technology
- hd video
- power supply
- cmos technology
- low power
- analog to digital converter
- synthetic aperture radar
- silicon on insulator
- sar images
- high definition
- metal oxide semiconductor
- single chip
- power management
- high speed
- data flow
- image reconstruction
- low voltage
- power dissipation
- sar imagery
- database
- sea ice
- pac man
- cmos image sensor
- high frequency
- real time
- linear array
- mixed signal
- automatic target recognition
- wide dynamic range
- parallel processing
- parameter estimation