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Jiansong Wan
ORCID
Publication Activity (10 Years)
Years Active: 2011-2024
Publications (10 Years): 4
Top Topics
Low Voltage
Transport Systems
Nm Technology
Delay Insensitive
Top Venues
ISSCC
Ann. Oper. Res.
Int. J. Prod. Res.
CICC
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Publications
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Jiansong Wan
,
Kanghoon Lee
,
Hayong Shin
Traffic pattern-aware elevator dispatching via deep reinforcement learning.
Adv. Eng. Informatics
61 (2024)
Xiaoqun Yu
,
Jiansong Wan
,
Guoyuan An
,
Xu Yin
,
Shuping Xiong
A novel semi-supervised model for pre-impact fall detection with limited fall data.
Eng. Appl. Artif. Intell.
132 (2024)
Yan Huang
,
Jiansong Wan
Hierarchical analysis of Chinese financial market based on manifold structure.
Ann. Oper. Res.
315 (2) (2022)
Jiansong Wan
,
Hayong Shin
Predictive vehicle dispatching method for overhead hoist transport systems in semiconductor fabs.
Int. J. Prod. Res.
60 (10) (2022)
Jan Mulder
,
Davide Vecchi
,
Yi Ke
,
Stefano Bozzola
,
Mark Core
,
Nitz Saputra
,
Qiongna Zhang
,
Jeff Riley
,
Han Yan
,
Mattia Introini
,
Sijia Wang
,
Christopher M. Ward
,
Jan R. Westra
,
Jiansong Wan
,
Klaas Bult
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.
ISSCC
(2015)
Jan R. Westra
,
Jan Mulder
,
Yi Ke
,
Davide Vecchi
,
Xiaodong Liu
,
Erol Arslan
,
Jiansong Wan
,
Qiongna Zhang
,
Sijia Wang
,
Frank M. L. van der Goes
,
Klaas Bult
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.
CICC
(2014)
Jan R. Westra
,
Jan Mulder
,
Yi Ke
,
Davide Vecchi
,
Xiaodong Liu
,
Erol Arslan
,
Jiansong Wan
,
Qiongna Zhang
,
Sijia Wang
,
Frank M. L. van der Goes
,
Klaas Bult
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.
ISSCC
(2014)
Davide Vecchi
,
Jan Mulder
,
Frank M. L. van der Goes
,
Jan R. Westra
,
Emre Ayranci
,
Christopher M. Ward
,
Jiansong Wan
,
Klaas Bult
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.
IEEE J. Solid State Circuits
46 (12) (2011)
Jan Mulder
,
Frank M. L. van der Goes
,
Davide Vecchi
,
Jan R. Westra
,
Emre Ayranci
,
Christopher M. Ward
,
Jiansong Wan
,
Klaas Bult
An 800MS/s dual-residue pipeline ADC in 40nm CMOS.
ISSCC
(2011)