An 800MS/s dual-residue pipeline ADC in 40nm CMOS.
Jan MulderFrank M. L. van der GoesDavide VecchiJan R. WestraEmre AyranciChristopher M. WardJiansong WanKlaas BultPublished in: ISSCC (2011)
Keyphrases
- cmos technology
- analog to digital converter
- silicon on insulator
- nm technology
- metal oxide semiconductor
- power consumption
- high speed
- single chip
- analog vlsi
- low cost
- processing pipeline
- amino acids
- low power
- power supply
- primal dual
- low voltage
- cmos image sensor
- pipeline architecture
- neural network
- focal plane
- delay insensitive
- hd video
- parallel processing
- control system