Davide Vecchi

Publication Activity (10 Years)

Years Active: 2001-2021
Publications (10 Years): 2

Top Topics

Delay Insensitive

Evolutionary History

Top Venues

Publications

Elena Casetta, Davide Vecchi
Species are, at the same time, kinds and individuals: a causal argument based on an empirical approach to species identity. Synth. 198 (12-S) (2021)
Davide Vecchi
Entrenchment implies that physiological and developmental processes are not organism-bound but still organism-centric. Adapt. Behav. 28 (1) (2020)
Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. ISSCC (2015)
Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. CICC (2014)
Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. ISSCC (2014)
Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. IEEE J. Solid State Circuits 46 (12) (2011)
Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC (2011)
Andrea Boni, Cristiano Azzolini, Davide Vecchi, Giovanni Chiorboli
Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCs. Circuits Syst. Signal Process. 28 (4) (2009)
Andrea Boni, Matteo Parenti, Davide Vecchi
Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS. IEEE Trans. Circuits Syst. II Express Briefs (6) (2006)
Giovanni Chiorboli, Silvia Dondi, Carlo Morandi, Davide Vecchi
DAC calibration by weighting capacitor rotation in a pipelined ADC. Circuits, Signals, and Systems (2005)
Cristiano Azzolini, Andrea Boni, Alessio Facen, Matteo Parenti, Davide Vecchi
Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technology. ISCAS (2) (2005)
Davide Vecchi, Cristiano Azzolini, Andrea Boni, Faouzi Chaahoub, Lorenzo Crespi
100-MS/s 14-b track-and-hold amplifier in 0.18-μm CMOS. ESSCIRC (2005)
Andrea Boni, Andrea Pierazzi, Davide Vecchi
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS. IEEE J. Solid State Circuits 36 (4) (2001)