Hamid Mahmoodi-Meimand

Publication Activity (10 Years)

Years Active: 2001-2006
Publications (10 Years): 0

Publications

Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC (2006)
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 14 (2) (2006)
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design (2006)
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE (2006)
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
Double-gate SOI devices for low-power and high-performance applications. ICCAD (2005)
Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS (2005)
Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
Dual-Edge Triggered Static Pulsed Flip-Flops. VLSI Design (2005)
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE (2005)
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD (2005)
Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
Low-power scan design using first-level supply gating. IEEE Trans. Very Large Scale Integr. Syst. 13 (3) (2005)
Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium (2005)
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI (2005)
Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. 13 (1) (2005)
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi
A high speed and leakage-tolerant domino logic for high fan-in gates. ACM Great Lakes Symposium on VLSI (2005)
Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
Pre-capturing static pulsed flip-flops. ISCAS (3) (2005)
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC (2005)
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED (2005)
Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED (2005)
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (12) (2005)
Hamid Mahmoodi-Meimand, Kaushik Roy
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2004)
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT (2004)
Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy
Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits 39 (2) (2004)
Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. CICC (2004)
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD (2004)
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
Statistical design and optimization of SRAM cell for yield enhancement. ICCAD (2004)
Hamid Mahmoodi-Meimand, Kaushik Roy
Dual-edge triggered level converting flip-flops. ISCAS (2) (2004)
Hamid Mahmoodi-Meimand, Kaushik Roy
Data-retention flip-flops for power-down applications. ISCAS (2) (2004)
Kauschick Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91 (2) (2003)
Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED (2003)
Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. 11 (6) (2002)
Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
High performance and low power FIR filter design based on sharing multiplication. ISLPED (2002)
Hamid Mahmoodi-Meimand, Ali Afzali-Kusha
Efficient power clock generation for adiabatic logic. ISCAS (4) (2001)