Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
Saibal MukhopadhyayHamid Mahmoodi-MeimandKaushik RoyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2005)
Keyphrases
- power consumption
- probability distribution
- random access memory
- engineering design
- knowledge based systems
- statistical analysis
- design process
- low power
- cmos technology
- circuit design
- design considerations
- learning environment
- information theoretic
- image enhancement
- high speed
- design principles
- modeling language
- low cost
- failure rate
- power supply
- genetic algorithm