A Novel Low-Power Scan Design Technique Using Supply Gating.

Swarup Bhunia Hamid Mahmoodi-Meimand Saibal Mukhopadhyay Debjyoti Ghosh Kaushik Roy

Published in: ICCD (2004)

Keyphrases

low power
single chip
power consumption
low power consumption
low cost
gate array
vlsi architecture
high speed
logic circuits
digital signal processing
cmos technology
power dissipation
power reduction
ultra low power
mixed signal
delay insensitive
wireless transmission
real time
nm technology