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Low-power scan design using first-level supply gating.
Swarup Bhunia
Hamid Mahmoodi-Meimand
Debjyoti Ghosh
Saibal Mukhopadhyay
Kaushik Roy
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
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low power
single chip
power consumption
low power consumption
low cost
high speed
logic circuits
vlsi architecture
digital signal processing
mixed signal
power dissipation
gate array
cmos technology
design methodology
real time
ultra low power
circuit design
high power
design considerations