A heuristic fault based optimization approach to reduce test vectors count in VLSI testing.
Vinod Kumar KheraR. K. SharmaA. K. GuptaPublished in: J. King Saud Univ. Comput. Inf. Sci. (2019)
Keyphrases
- test cases
- software testing
- combinatorial optimization
- test generation
- regression testing
- optimization algorithm
- optimization method
- test sequences
- fault diagnosis
- test data
- statistical tests
- fault model
- test suite
- signal processing
- global optimization
- optimization process
- testing process
- test case generation
- search algorithm
- model based testing
- test data generation
- integration testing
- heuristic methods
- fault detection
- optimization problems
- simulated annealing
- set of test cases
- genetic algorithm
- real time embedded systems
- code coverage
- feature vectors
- optimal solution