Yen-Jen Chang

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 12

Top Topics

Content Addressable

Convolutional Neural Network

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Emerg. Sel. Topics Circuits Syst.

Comput. Electr. Eng.

Publications

Yen-Jen Chang, Kun-Lin Tsai, Wei-Cheng Jiang, Meng-Kun Liu
Content-aware malicious webpage detection using convolutional neural network. Multim. Tools Appl. 83 (3) (2024)
Yen-Jen Chang, Ming-Hsin Lai, Chien-Ho Wang, Yu-Shun Huang, Jason Lin
Target-Aware Yield Prediction (TAYP) Model Used to Improve Agriculture Crop Productivity. IEEE Trans. Geosci. Remote. Sens. 62 (2024)
Yen-Jen Chang, Yi-Da Wu, Yu-Lin Liao, Chien-Ho Wang, Yen-Ching Wu
Modified YOLO network model for metaphase cell detection in antinuclear antibody images. Eng. Appl. Artif. Intell. 127 (Part B) (2024)
Yen-Jen Chang, Shih-Hsiang Chen
Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng
Data Retention-Based Low Leakage Power TCAM for Network Packet Routing. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Kun-Lin Tsai, Yen-Jen Chang, Chien-Ho Wang, Cheng-Tse Chiang
Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, Chun-Huo Hsiao
A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism. IEEE Access 8 (2020)
Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng, Meng-Rong Lu
Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment. Comput. Electr. Eng. 81 (2020)
Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, Tung-Chi Wu
Imprecise 4-2 compressor design used in image processing applications. IET Circuits Devices Syst. 13 (6) (2019)
Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, Yen-Jen Chang
Radix-4 adder design with refined carry. DSC (2017)
Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, Yen-Jen Chang
Low leakage mask vertical control TCAM for network router. APCCAS (2016)
Yen-Jen Chang, Tung-Chi Wu
Master-Slave Match Line Design for Low-Power Content-Addressable Memory. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Kun-Lin Tsai, Yen-Jen Chang, Yu-Cheng Cheng
Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2014)
Yen-Jen Chang, Hsiang-Yu Lu
Improving the performance of port range check for network packet filtering. ACM Trans. Design Autom. Electr. Syst. 19 (1) (2013)
Ya-Chun Lin, Yen-Jen Chang, Tung-Chi Wu
Low-power content-addressable memory design using a double match-line (DML) architecture. MWSCAS (2013)
Yen-Jen Chang, Kun-Lin Tsai, Hsiang-Jen Tsai
Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2013)
Yen-Jen Chang, Tung-Chi Wu
A low-power TCAM design using mask-aware match-line (MAML) technique. ACM Great Lakes Symposium on VLSI (2011)
Chuen-Horng Lin, Der-Chen Huang, Yung-Kuan Chan, Kai-Hung Chen, Yen-Jen Chang
Fast color-spatial feature based image retrieval methods. Expert Syst. Appl. 38 (9) (2011)
Yen-Jen Chang
Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table. IEEE Trans. Very Large Scale Integr. Syst. 18 (11) (2010)
Yen-Jen Chang
Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power. IEEE Trans. Circuits Syst. II Express Briefs (11) (2010)
Yen-Jen Chang
A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Jin-Wei Yang, Yen-Jen Chang
Low Power Selected Gating Frame Buffer (SGFB) Design. ESA (2009)
Yung-Feng Cheng, Yen-Jen Chang
A Novel High Performance Ternary CAM (TCAM) for LPM. ESA (2009)
Yen-Jen Chang
Exploiting frequent opcode locality for power efficient instruction cache. ACM Great Lakes Symposium on VLSI (2008)
Yen-Jen Chang, Yuan-Hong Liao
Hybrid-Type CAM Design for Both Power and Performance Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
Yen-Jen Chang, Maofeng Lan
Two New Techniques Integrated for Energy-Efficient TLB Design. IEEE Trans. Very Large Scale Integr. Syst. 15 (1) (2007)
Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan
Improve CAM power efficiency using decoupled match line scheme. DATE (2007)
Yen-Jen Chang
An Alternative Real-Time Filter Scheme to Block Buffering. VLSI Design (2006)
Yen-Jen Chang
An ultra low-power TLB design. DATE (2006)
Yen-Jen Chang
Lazy BTB: reduce BTB energy consumption using dynamic profiling. ASP-DAC (2006)
Yen-Jen Chang
An Energy-Efficient BTB Lookup Scheme for Embedded Processors. IEEE Trans. Circuits Syst. II Express Briefs (9) (2006)
Yen-Jen Chang, Feipei Lai
Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories. IEEE Micro 25 (4) (2005)
Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. Very Large Scale Integr. Syst. 12 (8) (2004)
Yen-Jen Chang, Yung-Ching Weng, Feipei Lai
Enhanced object management for high performance web proxies. SAC (2004)
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. DATE (2004)
Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai
Design and analysis of low-power cache using two-level filter scheme. IEEE Trans. Very Large Scale Integr. Syst. 11 (4) (2003)
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
A power-aware SWDR cell for reducing cache write power. ISLPED (2003)
Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
An Efficient Two-Level Filter Scheme for Low Power Cache. IWLS (2002)
Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Yen-Jen Chang, Feipei Lai
Paged cache: an efficient partition architecture for reducing power, area and access time. APCCAS (2) (2002)
Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. ICCD (2002)
Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai
Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) (2002)