Low-power content-addressable memory design using a double match-line (DML) architecture.
Ya-Chun LinYen-Jen ChangTung-Chi WuPublished in: MWSCAS (2013)
Keyphrases
- low power
- vlsi architecture
- high speed
- single chip
- cmos technology
- low cost
- power consumption
- low power consumption
- mixed signal
- logic circuits
- nm technology
- gate array
- power dissipation
- digital signal processing
- vlsi implementation
- real time
- low complexity
- cmos image sensor
- design process
- design considerations
- design methodology
- multi channel
- vlsi circuits
- content addressable memory