An Efficient Two-Level Filter Scheme for Low Power Cache.

Yen-Jen Chang Feipei Lai Shanq-Jang Ruan

Published in: IWLS (2002)

Keyphrases

low power
power consumption
high speed
low cost
single chip
deblocking filter
wireless transmission
vlsi architecture
high power
low power consumption
digital signal processing
logic circuits
cmos technology
image processing
mixed signal
main memory
signal processor
gate array
ultra low power