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Design and analysis of low-power cache using two-level filter scheme.
Yen-Jen Chang
Shanq-Jang Ruan
Feipei Lai
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2003)
Keyphrases
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low power
single chip
power consumption
low cost
logic circuits
low power consumption
high speed
high power
vlsi architecture
gate array
digital signal processing
design considerations
design methodology
real time
image sensor
hardware and software
main memory